PXB4340E Datasheet, PDF (88/185 Pages) Infineon Technologies AG – ICs for Communications

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Read/write Address E1_H
Value after reset 0000_H
This register configures the PHY side UTOPIA interfaces and the defines the LCI location.


Unused
Unused
UTP16 Unused UTPPAR

LCIMOD(1:0)

UTPCONF(1:0)
Bit(15:10)
LCIMOD(1:0)
Bit(7:5)
UTP16
Bit(3)
UTPPAR
UTPCONF(1:0)
Unused
Position of LCI up/downstream:
00
LCI(13:12) = UDF(7:6), LCI(11:0) = VPI(11:0)
01
LCI(13:12) = 00, LCI(11:0) = VPI
In this mode no ICC possible.
10
LCI(13:0) = VCI(13:0)
F4-OAM/User-Flow not supported.
11
Is not allowed, will be handled as ’10’.
Unused
Select 8- or 16-bit UTOPIA Data bus
0
8 bit data bus at PHY side.
1
16 bit data bus at PHY side.
Unused
Enables/disables parity check
0
Don’t check parity of PHY receive data.
1
Check parity of PHY receive data.
Configuration of mode at PHY side :
00
4 x 6 port
01
3 x 8 port
10
2 x 12 port
11
UTOPIA Level 1 (4 x 1 port)
Data Sheet
3-88
04.2000