PXB4340E Datasheet, PDF (131/185 Pages) Infineon Technologies AG – ICs for Communications

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11 CRDIF2N F5
2
17 Indication for a state transition from F5 RDI
failure state to F5 RDI normal state.
10 CRDID2F F5
2
16 Indication for a state transition from F5 RDI
defect state to F5 RDI failure state.
9
CAISF2N F5
2
15 Indication for a state transition from F5 AIS
failure state to F5 AIS normal state.
8
CAISD2F F5
2
14 Indication for a state transition from F5 AIS
defect state to F5 AIS failure state.
7 ’0’ always -
-
-
6 ’0’ always -
-
-
5
CLOCFAI F5
1
5 F5 LOC failure state.
4
CLOCDEF F5
1
4 F5 LOC defect state.
3
CRDIFAI F5
1
3 F5 RDI failure state.
2
CRDIDEF F5
1
2 F5 RDI defect state.
1
CAISFAI F5
1
1 F5 AIS failure state.
0
CAISDEF F5
1
0 F5 AIS defect state.
1) _{Refer to the external RAM (identical for up- and downstream RAM).}
2) _{For detailed explanation see section 3.9.1, page 98, section 3.9.2, page 104, section 3.9.3, page 110 and}
section 3.9.4, page 116.
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Also in normal operation the local controller checks all data collection entries, compares the
values with the given thresholds and if these are exceeded
• Activates AIS/RDI insertion and
• Informs network management
Optionally records of the e.g. last 15 minutes could be collected on-board for the last 24 hours.
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Events are unpredictable for the peripheral controller. These may be interrupts from the HW or
command messages received from the system controller .
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Such failures are e.g. line breaks or transmitter/receiver failure. They are detected by the PHY
device and usually signalled to the local controller by interrupt. If the failure is confirmed the local
controller
• sets the corresponding PHY error bit in a AOP register
to signal the failure to the ATM layer. All ensuing actions as generation of VP-AIS or VC-AIS cells
in forward direction as well as the insertion of VP-RDI or VC-RDI cells in backward direction are
done automatically by the scan mechanism.
Data Sheet
4-131
04.2000