PXB4340E Datasheet, PDF (126/185 Pages) Infineon Technologies AG – ICs for Communications

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This section describes the actions to be done by the microprocessor. For this purpose the
following network scenario is assumed (see also )LJXUHV   DQG  for reference):
• The OAM functions AIS/RDI/CC are always enabled for all connections (although the AOP
also supports enabling on a per-connection basis). Activating the CC function by default
avoids use of CC activation/deactivation cells.
• For all time-out values the recommended values of the standard [] are used.
• Performance monitoring is always initiated by the generating port (VHH )LJXUH ) using PM
activation cells. The respective endpoint loops a cell with ’activation request confirmed’ back
if a PM processor is available. If all 128 PM processors are in use the ’activation request
denied’ cell is sent back. The deactivation cell is always confirmed.
• PM data collection is always done on the port where the FM cells are generated, i.e. the BR
cells are evaluated and discarded there (the AOP supports PM data collection on any point
along the backward PM cell path).
• Segment borders are fixed to transmission lines (although the AOP supports the per-
connection definition of segment points).
• At originating segment points AIS/RDI monitoring for VPCs is enabled, i.e. at the entrance of
the network of an operator it is detected if a VPC is received fault-free or not. So the network
operator knows at any time the availability of his VPCs. Monitoring is not activated for VCCs,
as these are set-up only temporary.
All these assumptions facilitate OAM management by reducing the number of parameters to be
handled.
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For a normal read-modify-write access to a RAM, the following actions have to be done by the
microprocessor :
1. Write the data to the write transfer registers WDR0L..WDR13H (see VHFWLRQ  page
59).
2. Set the mask bits in the mask data registers MDR0L..MDR6H and WMASK (see VHFWLRQ
 page 60 and VHFWLRQ  page 61). Note that RAM words 0..6 are bitwise masked
with the MDR registers, RAM words 7..13 are masked completely by setting the
corresponding bit in register WMASK).
3. Write the LCI to the address register RMWADR (see VHFWLRQ  page 63).
4. Set the following bits in the read-modify-write control register RMWC (see VHFWLRQ 
page 62) : bits 5..4 (e.g. to ’01’ for external RAM), bit 2 equal to ’1’ for upstream or equal to
’0’ for downstream and bit 3 epual to ’1’, i.e. start of RMW.
5. The RMW is done when bit 3 of RMWC is set to ’0’ by the AOP.
6. Read the read transfer registers RDR0L..RDR13H (see VHFWLRQ  page 60).
RMW access on PM or DC RAM is the same as for the external RAM, besides that RMWADR
should have a value between 0 and 127 and for PMMAIN only registers WDR0L..WDR2H,
RDR0L..RDR2H, MDR0L..MDR2H are used. The entries 0..3 will be written to address LCI
defined by register RMWADR, the entries 4..7 to address LCI2 defined in entry 0. Note, that read
Data Sheet
4-126
04.2000