PXB4340E Datasheet, PDF (115/185 Pages) Infineon Technologies AG – ICs for Communications

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Bit 12
Bit 11..7
Bit 6
Bit 5
Bit 4
Bit 3..0
OAMMIS
1
Miss inserted OAM cell discarded. Reported with interrupt
DOAMIS.
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
CCCINS
0
Default, normal CC cell insertion.
1
Force insertion of F5 CC Cells for all activated CC flows;
period determined by MAXTS in register SCCONF1.
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
CARINS
1
Force insertion of F5 AIS Cells downstream (CIP=1).
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
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Bit 31
Bit 30
Bit 29
Bit 28
CEDCID(6:0)
CSDCID(6:0)
CPMTID(6:0)
CPMOID(6:0)
PAR
Dword parity protection. In normal operation write to 0. Should always
read as 0.
CEDCEN
Enable Data Collection on F5 End-to-End BR cells. Related identifier
CEDCID.
CSDCEN
Enable Data Collection on F5 Segment BR cells directly generated
from F5 segment FM cells. Related identifier CSDCID.
CTSDCEN
Enable Data Collection on terminated / intermediate F5 Segment BR
cells, related identifier CTSDCID in Dword2.
Identifier for Data Collection on F5 Segment BR cells. Related enable
CEDCEN.
Identifier for Data Collection on F5 Segment BR cells directly generated
from F5 segment FM cells. Related enable CSDCEN.
Identifier for a terminating F5 Segment or End-to-End FM flow. Related
enable CPMTEN in Dword0.
Identifier for an originating F5 Segment or End-to-End FM flow. Related
enable CPMOEN in Dword0.
Data Sheet
3-115
04.2000