PXB4340E Datasheet, PDF (113/185 Pages) Infineon Technologies AG – ICs for Communications

Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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CCCMEN
0
F5 CC monitoring disabled.
1
F5 CC monitoring enabled.
State transition to LOC failure state and out of LOC failure
state is reported by use of the µP interrupt DCSTTR.
CARIEN
0
F5 AIS or RDI Cell insertion disabled.
1
F5 AIS or RDI Cell insertion enabled.
Independent of the reason for cell generation (forced
insertion by ARINS, detected LOC or AIS state) AIS/RDI
cell generation is always controlled by this flag. Necessary
e.g. to suppress RDI at endpoints of multicast or
unidirectional connections.
CLOCFAI
F5 LOC failure state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
CLOCDEF
F5 LOC defect state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
CRDIFAI
F5 RDI failure state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
CRDIDEF
F5 RDI defect state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
CAISFAI
F5 AIS failure state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
CAISDEF
F5 AIS defect state. Initialize to 0 at connection setup. Do not change
by µP in normal operation.
Data Sheet
3-113
04.2000