PXB4340E Datasheet, PDF (162/185 Pages) Infineon Technologies AG – ICs for Communications

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80 _UTPHYCLK
81
PHY Clk frequency (nominal)
PHY Clk duty cycle
I_SYSCLK/2 52
40
60
82
PHY Clk peak-to-peak jitter
-
5
83
PHY Clk rise/fall time
-
2
84 _TXDATD
[15:0],
TXSOCD,
A>P Input setup to PHY Clk
4
-
85 _TXPRTYD,
TXENBD[0]
Input hold from PHY Clk
1
-
86 _{TXCLAVD[0] A<P Input setup to PHY Clk}
4
-
87
Input hold from PHY Clk
1
-
8QLW
MHz
%
%
ns
ns
ns
ns
ns
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80 _UTATMCLK
81
ATM Clk frequency (nominal)
ATM Clk duty cycle
I_SYSCLK/2 52
40
60
82
ATM Clk peak-to-peak jitter
-
5
83
ATM Clk rise/fall time
-
2
84 _RXDATD
A>P Input setup to ATM Clk
5
-
85 ^[15:0],
RXPRTYD
Input hold from ATM Clk
1
-
86 _RXSOCD,
A>P Input setup to ATM Clk
4
-
87 ^RXENBD[0]
Input hold from ATM Clk
1
-
88 _{RXCLAVD[0] A<P Input setup from ATM Clk}
4
-
89
Input hold from ATM Clk
1
-
8QLW
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
Data Sheet
6-162
04.2000