PXB4340E Datasheet, PDF (62/185 Pages) Infineon Technologies AG – ICs for Communications

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Read/write Address 47_H
Value after reset 0000_H


Unused
Unused
RAMSEL(1:0)
START
UP/DN
WRA


RDA
RAMSEL(1:0)
START
UP/DN
WRA
RDA
Select RAM for RMW access
00
PM data processing RAM
01
External RAM (up- or downstream selected with bit 2).
1x
PM data collection RAM
Command bit. Set =1 to start the RMW-access specified with bits 2, 4
and 5. Bit 3 is reset after execution of the command. RDR registers
should not be read before, otherwise it will result in unexpected values.
Selection of external RAM for RMW-Access:
0
Downstream-RAM.
1
Upstream-RAM.
Write all. Setting this bit together with the START bit sets all mask
register bits to one EHIRUH the RMW access. This results in a write
access of the whole entry. All Dwords of the specified entry are
overwritten. The mask bits remain cleared after the access. WRA is
reset to zero after execution of the RMW access.
Read all. Setting this bit together with the START bit sets all mask
register bits to zero EHIRUH the RMW access. This results in a read only
access. No data in the specified entry is modified. The mask bits remain
set after the access. RDA is reset to zero after execution of the RMW
access.
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Data Sheet
3-62
04.2000