PXB4340E Datasheet, PDF (59/185 Pages) Infineon Technologies AG – ICs for Communications

3;%  (
5HJLVWHU 'HVFULSWLRQ
 :ULWH 7UDQVIHU 5HJLVWHUV :'5/:'5+
Read/write Address 00_H..1B_H
Value after reset 0000_H
The write transfer registers are shown below with their mapping to the 32-bit Dwords 0..13.


13 ^{Register WDR13H / Address 1B}H
12 ^{Register WDR12H / Address 19}H
11 ^{Register WDR11H / Address 17}H
10 ^{Register WDR10H / Address 15}H
9 ^{Register WDR9H / Address 13}H
8 ^{Register WDR8H / Address 11}H
7 ^{Register WDR7H / Address 0F}H
6 ^{Register WDR6H / Address 0D}H
5 ^{Register WDR5H / Address 0B}H
4 ^{Register WDR4H / Address 09}H
3 ^{Register WDR3H / Address 07}H
2 ^{Register WDR2H / Address 05}H
1 ^{Register WDR1H / Address03}H
0 ^{Register WDR0H / Address 01}H



Register WDR13L / Address 1A_H
Register WDR12L / Address 18_H
Register WDR11L / Address 16_H
Register WDR10L / Address 14_H
Register WDR9L / Address 12_H
Register WDR8L / Address 10_H
Register WDR7L / Address 0E_H
Register WDR6L / Address 0C_H
Register WDR5L / Address 0A_H
Register WDR4L / Address 08_H
Register WDR3L / Address 06_H
Register WDR2L / Address 04_H
Register WDR1L / Address 02_H
Register WDR0L / Address 00_H
When accessing the external RAM bit 31 of each Dword controls the parity bit of the entry. If
bit 31=0 the correct parity bit is generated. If bit 31=1 the parity bit is inverted.
Data Sheet
3-59
04.2000