PXB4340E Datasheet, PDF (82/185 Pages) Infineon Technologies AG – ICs for Communications

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DMA buffer empty = 0 words in FIFO.
DMA buffer full ≥ 32 words in FIFO.
Currently processed LCI up- and downstream. Internal state for
debugging.
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Interrupt bits signal unpredictable events to the controlling microprocessor, e.g. errors. Each
interrupt bit signals a different event. Events which are associated to a certain connection, as
e.g. the misinserted OAM cell interrupt are stored additionally also in the external connection
RAM under the respective LCI entry. If one of these interrupt indications is set the corresponding
error might have occured for at least one or more connections. Thus the microprocessor has to
check all entries of the connection RAM dedicated to the respective direction for the indicated
error.
To clear interrupt bits the microprocessor must write a ’1’ to the respective bit. Writing a ’0’ has
no effect. This behaviour simplifies interrupt management by separate interrupt routines. After a
HW interrupt more than one interrupt bit might be set. Then each interrupt routine can clear the
respective bit separately after having checked or corrected the interrupt cause.
Data Sheet
3-82
04.2000