PXB4340E Datasheet, PDF (58/185 Pages) Infineon Technologies AG – ICs for Communications

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RAM entry k
1 Read Transfer
2 Write Transfer
32
3
2
1
0
32
13
Read Transfer
Registers RDR
0
H
L
32
13
Write Transfer
Registers WDR
0
H
L
1
Select
WMASK
Bit 0..6
6 13
07
Mask Registers ⁶
MDR
0
H
L
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The address of the selected entry is given in register RMWADR. Register bits for specifying the
target RAM and initiating the transfer are contained in the read-modify-write control register
RMWC. This register also contains command bits for setting or clearing all mask register bits.
Read and write register sets RDR and WDR contain 14 Dwords in 28 registers. For simplification
the mask register set is slightly different: MDR0..6 have a one-to-one bit mapping with RDR0..6
and WDR0..6. For RDR7..13 and WDR7..13 one single mask bit for each Dword is provided in
the WMASK register, bits 0..6.
When accessing RAM entries with less than 14 Dwords (see 7DEOH ) only the lower registers
of RDR, WDR and MDR are involved, e.g. for accesses to the 8-Dword size entries of the
external connection tables RDR0..7, WDR0..7, MDR0..6 and bit 0 of WMASK are involved.
For accesses to the different RAMs the RDR and WDR register bits have different meaning. This
is described for each target RAM in the mapping tables (see VHFWLRQ ).
Data Sheet
3-58
04.2000