PXB4340E Datasheet, PDF (167/185 Pages) Infineon Technologies AG – ICs for Communications

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Timing of the Synchronous Static RAM Interfaces is simplified as all signals are referenced to
the rising edge of SYSCLK. In )LJXUH , it can be seen that all signals output by the
PXB 4340 E AOP have identical delay times with reference to the clock. When reading from the
RAM, the PXB 4340 E AOP samples the data within a window at the rising clock edge.
SYSCLK
RSC, RADV,
RADR(17:0), RGW,
RCE, ROE
RDAT(31:0), output
RDAT(31:0), input
100
101
102
103
104
105 106
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1R 3DUDPHWHU
0LQ
100
100A
101
7_SYSCLK : Period SYSCLK
)_SYSCLK : Frequency SYSCLK
SYSCLK Low Pulse Width
19.2
7
102 _{SYSCLK High Pulse Width}
7
103 _{Delay SYSCLK rising to RSC, RADV,}
2
RADR(17:0), RGW, RCE, ROE
104 _{Delay SYSCLK rising to RDAT Output}
2
105 _{Setup time RDAT Input before SYSCLK 6}
rising (read cycles)
106 _{Hold time RDAT Input after SYSCLK rising 1.5}
(read cycles)
/LPLW 9DOXHV
7\S
0D[
52
15
15
8QLW
ns
MHz
ns
ns
ns
ns
ns
ns
Data Sheet
6-167
04.2000