PXB4340E Datasheet, PDF (22/185 Pages) Infineon Technologies AG – ICs for Communications

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The PXB 4340 AOP provides full standardized OAM functionality of the ATM layer in one device,
covering the functions Fault Management (AIS, RDI, CC, LB) and Performance Monitoring (FM
flow, BR flow, Data Collection). It has STM-4/OC-12 equivalent throughput in upstream and
downstream direction.
The AIS, RDI, CC mechanism can be applied to a range of up to 16K (=16384) connections.
Performance Monitoring can be done for 128 connections simultaneously with each connection
selectable from up- or downstream direction. Loopback functionality can be applied to the full
range of up to 16K connections (see VHFWLRQ  page 27 and VHFWLRQ  page 34).
Data cells are transferred via industry standard Level 2, single-port/ multi-port UTOPIA
interfaces based on cell level handshake. They can be adjusted for 8-bit or 16-bit data transfer.
The ATM side UTOPIA interface is operating in slave mode, the PHY side UTOPIA interface in
master mode. The PHY number of a cell is transported transparently through the chip, i.e. a cell
input at an UTOPIA receive interface with the PHY number P is output at the corresponding
UTOPIA transmit interface with the same PHY number P. Note that the PHY number is not the
UTOPIA address, but contains address and handshake line pair information (see VHFWLRQ )
Two 32 bit external SSRAM blocks are provided for OAM data storage for each connection.
Their size is depending on the number of supported connections (see VHFWLRQ  page 139).
Chip control is performed by a standard 16-bit asynchronous microprocessor interface (e.g. for
80386EX). The microprocessor can access the external RAMs any time during operation. This
is necessary for connection set up/release, data read/modify/write and configuration adjustment.
The external RAM is not memory mapped into the microprocessor address range. Accesses
occur via a transfer register set using transfer commands or via DMA (see VHFWLRQ  page
141). All functions are supported to a great extent in HW, so that SW effort is minimized.
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Data throughput is depending on the chip operating clock SYSCLK, which is used for the chip
core and the external SSRAMs. The PXB 4340 AOP needs 32 cycles of the SYSCLK to process
one ATM cell. Thus in 32 cycles 64 octets are transported through the chip for a 53 octet ATM
cell, giving a penalty of 53/64. Hence the ATM cell throughput is:
ATM cell throughput[Mbit/s] = SYSCLK[MHz] x 16 x 53/64 = SYSCLK[MHz] x 13.25
For a frequency of 51.84 MHz the throughput is 686.88 Mbit/s. The 51.84 MHz are easy to
generate, as this is 1/3 of 155.52 MHz, the generic SDH/SONET frequency.
The clock of the UTOPIA interfaces is independent of SYSCLK. It should be less or equal to the
SYSCLK frequency. This is not a restriction, as the transfer time for a cell in the UTOPIA
interface is only 27 clock cycles.
Data Sheet
2-22
04.2000