PXB4340E Datasheet, PDF (8/185 Pages) Infineon Technologies AG – ICs for Communications

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Chipset configuration for main ATM layer functionality . . . . . . . . . . . . . . . . . . . 11
Chipset configuration for main ATM layer functionality plus full OAM . . . . . . . . 12
Chipset configuration for main ATM layer functionality plus full OAM
and arbitrary header translation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Miniswitch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Line card configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Location of PXB 4340 E AOP on a Switch Port . . . . . . . . . . . . . . . . . . . . . . . . . 18
Symbol for Switch with AOPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VP Level OAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VC Level OAM Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
VC Endpoint inside the Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Cell Buffers in PXB 4340 AOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Thresholds in UTOPIA cell buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pointer Structure of up- and downstream OAM Tables . . . . . . . . . . . . . . . . . . . 26
Example for Line Failure Notification via AIS cells . . . . . . . . . . . . . . . . . . . . . . . 28
VP-AIS/RDI-Flow (F4-AIS/RDI-Flow) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
AIS State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
RDI State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Example for Misrouting Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
F4 segment CC Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Continuity Check Cell Generation State Diagram . . . . . . . . . . . . . . . . . . . . . . . 33
Continuity Check Evaluation State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Example of F4 End-to-End Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . 36
Example of F5 Segment Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . . 37
Example of F4 End Point Loopback Processing . . . . . . . . . . . . . . . . . . . . . . . . 38
PM Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PM Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Example for adjacent PM Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Effect of CC cells on AIS recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Access to internal or external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Scan Mechanism with OAM and/or DMA Function . . . . . . . . . . . . . . . . . . . . . . 49
Read-modify-write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Performance Monitoring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Standardized UTOPIA cell format (16-bit)
all fields according to standards, unused octets shaded . . . . . . . . . . . . . . . . . 136
Proprietary UTOPIA cell format (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Upstream receive UTOPIA example for 4 x 6 PHYs . . . . . . . . . . . . . . . . . . . . 137
Upstream or downstream RAM interface using 2 Mbits RAMs . . . . . . . . . . . . 139
Upstream or downstream RAM Interface using 1 Mbit RAMs . . . . . . . . . . . . . 140
Example of Execution Timing for Read Cycles (Burst Mode) . . . . . . . . . . . . . . 141
Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Input/Output Waveform for AC Measurements . . . . . . . . . . . . . . . . . . . . . . . . 153
Microprocessor Interface Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Microprocessor Interface Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Microprocessor DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Data Sheet
0-8
04.2000