PXB4340E Datasheet, PDF (57/185 Pages) Infineon Technologies AG – ICs for Communications

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These registers are provided for data transfer to and from the external connection RAMs or the
internal RAMs.Two internal RAMs are provided, one for PM data processing and one for the
collection of analysed PM results. Both PM RAMs are shared for up- and downstream direction.
The entries in each RAM have different sizes as shown in 7DEOH .
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Upstream connection RAM
Downstream connection RAM
PM processing data
PM data collection
External
External
On-chip
On-chip
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4 - 16k*
8
4 - 16k*
8
128
3
128
14
* Depending on external RAM size
There is only one single RAM access type, the read-modify-write transfer shown in ILJXUH .
It consists of two steps: in the first step all data from the specified RAM entry is transferred into
the read register set RDR. In the second step the data is written back again. It can be either the
original data or new data specified in the write register set WDR. The decision if original or new
data is written to the RAM entry is done via the mask register set MDR and the mask register
WMASK. For the lower 7 Dwords of an entry the source of each single bit can be individually
selected by the corresponding bit of the respective MDR register (bit-by-bit basis), for the upper
7 Dwords one single bit of WMASK selects the source for a whole Dword.
Data Sheet
3-57
04.2000