PXB4340E Datasheet, PDF (139/185 Pages) Infineon Technologies AG – ICs for Communications

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The AOP uses external, synchronous, static RAM (SSRAM) for the storage of connection
related OAM data. Two identical SSRAM interfaces are provided, one for each direction. The
SSRAM chips are operated with the system clock of up to 52 MHz.
All memory entries are protected with a parity bit at the MSB location.
The size of the SSRAM is depending on the number of supported connections: 8 dwords of 32-
bit are required per connection. Using SSRAM devices of 1 Mbit or 2 Mbit size, i.e. 32 K x 32 bit
and 64 K x 32 bit, respectively, the possible memory configurations are:
• 2 x 2 Mbit or 4 x 1 Mbit SSRAM for 16384 connections
• 1 x 2 Mbit or 2 x 1 Mbit SSRAM for 8192 connections
• 1 x 1 Mbit SSRAM for 4096 connections
These are the values for one direction. Both up- and downstream external memory should
always be configured symmetrical. The selection 1 Mbit or 2 Mbit SSRAM chips is done via
register bits. )LJXUH  shows an example of maximum RAM size with two 2 Mbit devices,
ILJXUH  shows an example of maximum RAM size with four 1 Mbit devices.
x = U for upstream, D for downstream RAM
2x2M configuration
RDATx(31:0)
RCE3x
IO(31:0)
A( 15)
1
0
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RADRx(14:0)
A(14:0)
RADVx
ROEx
RGWx
ADV
OE
GW
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RCE1x
RCE0x
RSCx
+3.3 V
10 kΩ
CLK
CE of RAM No. 1
CE of RAM No. 0
ADSC
ADSP
. [ ELW
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+3.3 V 10 kΩ
BWE
SYSCLK
+3.3 V
GND
10 kΩ
1 kΩ
GND
226Ω
CE2
CE2
BW1
BW2
BW3
BW4
MODE
ZZ
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Data Sheet
5-139
04.2000