PXB4340E Datasheet, PDF (165/185 Pages) Infineon Technologies AG – ICs for Communications

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80 _UTPHYCLK
81
PHY Clk frequency (nominal)
PHY Clk duty cycle
I_SYSCLK/2 52
40
60
82
PHY Clk peak-to-peak jitter
-
5
83
PHY Clk rise/fall time
-
2
84 _TXDATD
[15:0],
TXSOCD,
A>P Input setup to PHY Clk
4
-
85 _TXPRTYD,
TXENBD
[3:0],
TXADRD
[3:0]
Input hold from PHY Clk
1
-
86 _TXCLAVD
A<P Input setup to PHY Clk
4
-
87 ^[3:0]
Input hold from PHY Clk
1
-
88
Singnal going low impedance to 4
-
PHY Clk
89
Singnal going high impedance to 0
-
PHY Clk
90
Singnal going low impedance 1
-
from PHY Clk
91
Singnal going high impedance 1
-
from PHY Clk
8QLW
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
6-165
04.2000