PXB4340E Datasheet, PDF (107/185 Pages) Infineon Technologies AG – ICs for Communications

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Bit 7
Bit 6
Bit 5
Bit 4..0
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
PARINS
1
Force insertion of F4 AIS Cells upstream. Used e.g. for
AIS insertion due to VPC performance degrade
(determined by PM function).
Initialize to 1 at connection setup. Do not change by µP in normal
operation.
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
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Bit 31
Bit 30..15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
PAR
Dword parity protection. In normal operation write to 0. Should always
read as 0.
Initialize to 0 at connection setup. Do not change by µP in normal
operation.
PICCEN
1
Enable Internal Continuity check, in upstream direction
originating ICC is enabled.
PSCCTEN
1
Terminate a F4 Segment Continuity Check.
Should only be enabled at a F4 TSP (PTSP=0).
PECCTEN
1
Terminate a F4 End-to-End Continuity Check.
Should only be enabled at a F4 TEP (PIP=0).
PSCCOEN
1
Originate a F4 Segment Continuity Check. Should only be
enabled at a F4 OSP (POSP=1).
Reserved, set to 0.
PRDIMEN
0
F4 RDI monitoring disabled.
1
F4 RDI monitoring enabled.
State transition to RDI failure state and out of RDI failure
state is reported by use of the interrupt UPSTTR.
Data Sheet
3-107
04.2000