PXB4340E Datasheet, PDF (10/185 Pages) Infineon Technologies AG – ICs for Communications

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OAM Functionality Determined by Layer Point Configuration . . . . . . . . . . . . . . 19
AOP Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Internal and external RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Cell Filter Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SCAN periods for a core clock of 51.84 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Bit Mapping for "Compressed" DMA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
UTOPIA polling modes.
The numbers indicate the offset which is added to the PHY number. . . . . . . . 138
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Microprocessor Interface Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Microprocessor Interface Read Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Microprocessor DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Transmit Timing Upstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 161
Receive Timing Upstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 161
Transmit Timing Downstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Singel PHY) . . . . . . . . . . . . . . . . . 162
Receive Timing Downstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Single PHY) . . . . . . . . . . . . . . . . . 162
Transmit Timing Upstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 163
Receive Timing Upstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 164
Transmit Timing Downstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 165
Receive Timing Downstream
(16-Bit Data Bus, 50 MHz at Cell Interface, Multi-PHY) . . . . . . . . . . . . . . . . . . 166
SSRAM Interface AC Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Cell Filter Detecor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Boundary-Scan Test Interface AC Timing Characteristics . . . . . . . . . . . . . . . . 170
Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Layer Point Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Data Sheet
0-10
04.2000