PXB4340E Datasheet, PDF (111/185 Pages) Infineon Technologies AG – ICs for Communications

Bit 24
Bit 23
Bit 22
Bit 20
Bit 19
LCI2(13:0)
PN(4:0)
3;%  (
5HJLVWHU 'HVFULSWLRQ
DISF5
0
Enable F5 processing, default.
1
Disable F5 processing. All F5 OAM cells are discarded.
CTSP
0
No F5 Terminating Segment Point.
1
F5 Terminating Segment Point.
COS
0
No F5 Originating Segment Point.
1
F5 Originating Segment Point. Do not adjust at F5 TEP.
CIP
0
F5 Terminating End Point (TEP).
1
F5 Intermediate Point.
VCON
0
Connection not activated, cells for this LCI are discarded.
1
Connection activated.
Pointer to the VP connection data of the actual VCC. F4 pointer in
ILJXUH  ). Meaning of bits 18..5 depends on bit field ’lcimod’ in
register UTCONF1.
PHY Number associated with this LCI. Used for PHY specific RDI cell
generation.
Data Sheet
3-111
04.2000