PXB4340E Datasheet, PDF (78/185 Pages) Infineon Technologies AG – ICs for Communications

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DMAEN
MODE
INDEX(2:0)
Enable MPDREQ output signal:
0
MPDREQ is always tristate and MPDACK is not
evaluated.
1
MPDREQ gets low impedance if DMA is requested,
otherwise tristate. MPDREQ is MPDACK controlled.
Selects standard DMA or compressed DMA
0
Standard DMA: 32 bit RMW operation on Dword of LCI
entry selected with INDEX(2:0) using DWDR and DMR.
1
Compressed DMA: 32 bit RMW operation on all interrupt
relevant flags in LCI entry, no influence of DWDR, for bit
mapping see VHFWLRQ 4.1.6.1.
Selects which word (0..7) in the LCI table is object of the RMW
operation of standard DMA. INDEX is don’t care in compressed mode
(MODE=1).
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Read/write Address B8_H
Value after reset 0275_H

Unused

MAXTR(3:0)

MAXTS(1:0)

CCDEFMAX(3:0)
MAXTS(1:0)
MAXTR(3:0)
CCDEFMAX(3:0)
Time for generation of CC cells if no user cell has arrived in the CC
generation. Counted in multiples of SCAN cycles (typ. 500 ms).
Time for transition from normal operation to LOC defect state in the CC
evaluation. Counted in multiples of SCAN cycles (typ. 500 ms).
Time for transition from LOC defect to LOC failure state in the CC
evaluation. Counted in multiples of SCAN cycles (typ. 500 ms).
Data Sheet
3-78
04.2000