PXB4340E Datasheet, PDF (157/185 Pages) Infineon Technologies AG – ICs for Communications

3;%  (
(OHFWULFDO &KDUDFWHULVWLFV
80ns
ASIC not ready ASIC
=> one more T2 ready
PH2 PH1 PH2 PH1 PH2 PH1 ^PH2
386EX:CLK2
386EX:CLKOUT
T1
T2
T2
386EX:RD
386EX:DRE
386EX:DACK




+30ns RD output delay
Note:
+40ns synchronisation in ASIC
Time values given in this figure are
+20ns DRE output delay
example values and not tested in
production.
-80ns async DRE sampling before READY
200ns
)LJXUH  0LFURSURFHVVRU '0$ ,QWHUIDFH
7DEOH  0LFURSURFHVVRU '0$ LQWHUIDFH
1R 3DUDPHWHU
0LQ
40
Rising edge of MPDREQ after MPRD low 1
41
MPDREQ driven high before high
1
impedance
42
Interval between MPDREQ active
20
phases
(in case of successive accesses)
43
Interval between MPDACK inactive and 20
subsequent MPDREQ active
44
MPDREQ inactive before MPRDY active 5
(in case the DMA FIFO gets empty during
the current read access)
/LPLW 9DOXHV
7\S
0D[
3
1
5
8QLW
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
Data Sheet
6-157
04.2000