PXB4340E Datasheet, PDF (148/185 Pages) Infineon Technologies AG – ICs for Communications

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Pin Definitions and Functions
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FPCT2D
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V23
FPCT1D
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W26
FPCT2U
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W24
FPCT1U
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Cell Filter 2 detector output downstream. In case
of match a high pulse of 30 SYSCLK cycles is
output. Minimum low period between 2 pulses is 2
SYSCLK cycles.
Cell Filter 1 detector output downstream. In case
of match a high pulse of 30 SYSCLK cycles is
output. Minimum low period between 2 pulses is 2
SYSCLK cycles.
Cell Filter 2 detector output upstream. In case of
match a high pulse of 30 SYSCLK cycles is
output. Minimum low period between 2 pulses is 2
SYSCLK cycles.
Cell Filter 1 detector output upstream. In case of
match a high pulse of 30 SYSCLK cycles is
output. Minimum low period between 2 pulses is 2
SYSCLK cycles.
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AF24 ¹⁾
TDI
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AC14 ¹⁾
TCK
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AD25 ¹⁾
TMS
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AD26 ¹⁾
TRST
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AE26
TDO
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Test data input;
this pin has an internal pull-up resistor and need
not to be connected for normal operation.
Test clock;
this pin has an internal pull-up resistor and need
not to be connected for normal operation.
Test mode select
this pin has an internal pull-up resistor and need
not to be connected for normal operation.
TAP Controller Reset
this pin has an internal pull-down resistor and
need not to be connected for normal operation.
If connected it must be driven to V_SS for normal
operation.
Test data output;
need not to be connected for normal operation.
Data Sheet
5-148
04.2000