PXB4340E Datasheet, PDF (138/185 Pages) Infineon Technologies AG – ICs for Communications

3;%  (
,QWHUIDFHV
7DEOH 
8723,$ SROOLQJ PRGHV
7KH QXPEHUV LQGLFDWH WKH RIIVHW ZKLFK LV DGGHG WR WKH 3+< QXPEHU
0RGH  [  0RGH  [ 
0RGH  [ 
/HYHO  0RGH
EN0 / CLAV0
0
0
0
0
EN1 / CLAV1
12
8
6
0
EN2 / CLAV2
do not connect 16
12
0
EN3 / CLAV3
do not connect do not connect 18
0
The poll cycle is identical in all modes, i.e. the address lines output all addresses from 0 to 11
during one cell cycle. In one polling cycle all PHYs are polled. If the address is greater than the
number of PHYs at the device, the associated CLAVx is set to 0. The real PHY number depends
on the selected mode. The polling sequence of the next polling cycle depends on the current
transmitting PHY, e.g. if PHY5 is the current transmitter the next polling sequence is as follows:
PHY6,PHY7,...,PHY11,PHY1,PHY2,...,PHY5. In this case, PHY6 has the highest priority and
PHY5 the lowest. PHY5 is polled at byte 48 of the payload only when no other PHY is selected.
The selection of the next device also depends on the current device. If the current transmitter is
from device 2, the next polling cycle starts with the device 3 (highest priority), then device 4,
device 1 and device 2 (lowest priority).
• In Level 1 mode the PHY numbers are identical to the CLAV/EN group: 0, 1, 2, 3.
• It is the users responsibility to program the PHY numbers in a way that ambiguous PHY
numbers inside the ATM layer device are avoided.
• The mode selection can be done independently for the PHY side and the ATM side UTOPIA
interface (see VHFWLRQ  page 87 and VHFWLRQ  page 88).
• If less than or equal to 12 PHYs are to be polled, mode 2 x 12 should only be used with the
CLAV0/EN0 pair connected. This minimizes the number of interconnection lines between the
chips.
Examples:
1. One PHY device, e.g. a 622 Mbit/s PHY: 16-bit bus width, address lines unconnected,
RxCLAV0/RxEN0 and TxCLAV0/TxEN0 signal pairs connected, all other CLAVx/ENx pairs
unconnected (Level 1 Mode).
2. 4 PHY devices 155.52 Mbit/s PHYs: 16-bit bus width, address lines unconnected, all 4
CLAVx/ENx pairs connected, one to each PHY device.
3. 4 PHY devices of 6-fold 25.6 Mbit/s PHYs: 16-bit bus width, address and all 4 CLAVx/ENx
pairs connected, one to each PHY device (Mode 4x6, see ILJXUH ). The 4 CLAVx/ENx
lines are connected one-to-one to 4 PHY devices, each containing 6 PHYs of 25.6 Mbit/s.
In this example the maximum number of 24 PHYs is connected. The AOP gets 4 CLAVx
signals with each polled address. All PHY devices have the addresses 0..5 assigned to
their PHYs. Addresses greater than 5 always return CLAVx=0 when polled. In order to
distinguish the PHYs the UTOPIA interface of the AOP adds offset numbers, e.g. 6, 12 and
18 in mode 4x6, to the PHY numbers from PHY device 1, 2 and 3, respectively. Then within
the ATM layer device the PHY numbers range from 0..23 without ambiguity.
4. 4 PXB 4220 IWE8s: 8-bit bus width, address bus unconnected, all 4 CLAVx/ENx pairs
connected, one to each IWE8 (this mode requires the PXB 4350 E ALP).
Data Sheet
5-138
04.2000