PXB4340E Datasheet, PDF (164/185 Pages) Infineon Technologies AG – ICs for Communications

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80 _UTPHYCLK
81
PHY Clk frequency (nominal)
PHY Clk duty cycle
I_SYSCLK/2 52
40
60
82
PHY Clk peak-to-peak jitter
-
5
83
PHY Clk rise/fall time
-
2
84 _RXENBU
[3:0],
A>P Input setup to PHY Clk
4
-
85 RXADRU
[3:0]
Input hold from PHY Clk
1
-
86 _RXDATU
A<P Input setup to PHY Clk
5
-
87 ^[15:0],
RXPRTYU
88
Input hold from PHY Clk
1
-
Signal going low impedance to 5
-
PHY Clk
89
Signal going high impedance to 0
-
PHY Clk
90
Signal going low impedance from 1
-
PHY Clk
91
Signal going high impedance 1
-
from PHY Clk
86 _RXSOCU,
A<P Input setup to PHY Clk
4
-
87 ^RXCLAV
[3:0]
88
Input hold from PHY Clk
1
-
Signal going low impedance to 4
-
PHY Clk
89
Signal going high impedance to 0
-
PHY Clk
90
Signal going low impedance from 1
-
PHY Clk
91
Signal going high impedance 1
-
from PHY Clk
8QLW
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
6-164
04.2000