PXB4340E Datasheet, PDF (135/185 Pages) Infineon Technologies AG – ICs for Communications

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The AOP has one UTOPIA receive interface and one UTOPIA transmit interface with master
capability at the PHY side and one receive and transmit interface with slave capability at the
ATM side (ILJXUH ). The interfaces are compliant to the UTOPIA Level 1 and 2 specification
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• bus width is selectable either 8 or 16 bit
• single-PHY or multi-PHY configurations
• PHY number enhancement option, see specification UTOPIA Level 2 Appendix 1.
PHY
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ATM
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PHY
(P)
ATM
(A)
RXDATU(15:0)
RXSOCU
RXPRTYU
RXCLAVU(3:0)
RXENBU(3:0)
RXADRU(3:0)
TXDATU(15:0)
TXSOCU
TXPRTYU
TXCLAVU(3:0)
TXENBU(3:0)
TXADRU(3:0)
UTPHYCLK
TXDATD(15:0)
TXSOCD
TXPRTYD
TXCLAVD(3:0)
TXENBD(3:0)
TXADRD(3:0)
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UTATMCLK
RXDATD(15:0)
RXSOCD
RXPRTYD
RXCLAVD(3:0)
RXENBD(3:0)
RXADRD(3:0)
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Data Sheet
5-135
04.2000