PXB4340E Datasheet, PDF (156/185 Pages) Infineon Technologies AG – ICs for Communications

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For DMA operation the MPDREQ signal is necessary. It indicates that at least one more word is
available within the AOP DMA buffer. When the microprocessor reads the last word in the buffer
(DMAR register) it must be ensured that the MPDREQ signal is updated early enough to prohibit
another read to the DMAR register.
With asynchronous sampling of the microprocessor MPDREQ input, MPDREQ has to be
updated at least 1 CLKOUT cycle before the MPRDY gets active (386EX User manual, "12.2.5
Ending DMA Transfers", page 12-11). In AOP MPDREQ update is done 5 SYSCLK cycles (=
96ns at 51.84 Mhz) before MPRDY. With 25 Mhz microprocessor clock (CLK2) the CLKOUT
period (twice the CLK2 period) of 80 ns is satisfied. Less than 25 Mhz microprocessor clock
frequency may cause problems.
If MPDREQ gets inactive the AOP waits for MPDACK = ’high’, afterwards additional 20 SYSCLK
cycles (about 400ns) are spent until MPDREQ will become active again. This minimum gap was
introduced to ensure co-operation with the 80386EX internal DMA controller.
For distinction of 2 successive read cycles the read signal must be ’1’ for at least 1 SYSCLK
cycle, the chip select signal may remain active.
This ’command inactive time’ is necessary for all adjacent microprocessor read and write
accesses.
Data Sheet
6-156
04.2000