PXB4340E Datasheet, PDF (84/185 Pages) Infineon Technologies AG – ICs for Communications

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Bit 4
(Bit 3..0)
Bit 3
Bit 2
Bit 1
Bit 0
DBERR DMA Buffer Overflow or Underflow.
These bits indicate important transitions of AIS, RDI or CC state
diagrams (see )LJXUHV 17, 18 and 22) for any connection with the
respective functionality enabled. These are collection interrupts of the
respective connection specific flags in the external RAM:
DCSTTR
Downstream VC-related state transition occurred, i.e. one
of the bits 14..19 of Dword2 in downstream external RAM
entry set (see VHFWLRQ 3.9.3.3).
UCSTTR
Upstream VC-related state transition occurred, i.e. one of
the bits 14..19 of Dword2 in upstream external RAM set
(see VHFWLRQ 3.9.1.3).
DPSTTR
Downstream VP-related state transition occurred, i.e. one
of the bits 22..27 of Dword4 in downstream external RAM
set (see VHFWLRQ 3.9.4.1).
UPSTTR
Upstream VP-related state transition occurred, i.e. one of
the bits 22..27 of Dword4 in upstream external RAM set
(see VHFWLRQ 3.9.2.1).
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Read/write Address D1_H
Value after reset 0000_H
Bit 15:9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
SCTOUT Time-out for Scan processing within SCP.
Upstream Loopback cell discarded.
Downstream Loopback cell discarded.
Cell received for an invalid connection (VCON=0) upstream. VCON is
bit19 in Dword0 of upstream RAM (see VHFWLRQ 3.9.1.1).
Cell received for an invalid connection (VCON=0) downstream. VCON
is bit19 in Dword0 of downstream RAM (see VHFWLRQ 3.9.3.1).
RAM-Parity error occurred upstream.
RAM-Parity error occurred downstream.
UOAMIS
Mis-inserted OAM cell detected upstream. This indication
is also stored per connection in bit 12 of Dword2 in the
upstream external RAM.
DOAMIS
Mis-inserted OAM cell detected downstream. This
indication is also stored per connection in bit 12 of Dword2
in the downstream external RAM.
Data Sheet
3-84
04.2000