HD6433802H Datasheet, PDF (98/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
CCR I bit ← 1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
Clear interrupt request flag to 0
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
CCR I bit ← 0
Interrupt mask cleared
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
3.4.3 Interrupt Request Flag Clearing Method
Use the following recommended method for flag clearing in the interrupt request registers (IRR1,
IRR2, and IWPR).
Recommended Method: Perform flag clearing with only one instruction. Either a bit
manipulation instruction or a data transfer instruction in bytes can be used. Two examples of
coding for clearing IRRI1 (bit 1 in IRR1) are shown below:
• BCLR #1,@IRR1:8
• MOV.B R1L,@IRR1:8 (Set B’11111101 into R1L in advance)
Malfunction Example: When flag clearing is performed with several instructions, a flag, other
than the intended one, which was set while executing one of those instructions may be accidentally
cleared, and thus cause incorrect operations to occur.
An example of coding for clearing IRRI1 (bit 1 in IRR1), in which IRRI0 is also cleared and the
interrupt becomes invalid is shown below.
MOV.B @IRR1:8,R1L
AND.B #B’11111101,R1L
MOV.B R1L,@IRR1:8
At this point, IRRI0 is 0.
IRRI0 becomes 1 here.
IRRI0 is cleared to 0.
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