HD6433802H Datasheet, PDF (79/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

3.3.2 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name
Abbreviation R/W
IRQ edge select register
IEGR
R/W
Interrupt enable register 1
IENR1
R/W
Interrupt enable register 2
IENR2
R/W
Interrupt request register 1
IRR1
R/W*
Interrupt request register 2
IRR2
R/W*
Wakeup interrupt request register
IWPR
R/W*
Wakeup edge select register
WEGR
R/W
Note: * Write is enabled only for writing of 0 to clear a flag.
Initial Value
—
—
—
—
—
H'00
H'00
Address
H'FFF2
H'FFF3
H'FFF4
H'FFF6
H'FFF7
H'FFF9
H'FF90
1. IRQ edge select register (IEGR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
IEG1 IEG0
Initial value
1
1
1
—
—
—
0
0
Read/Write
—
—
—
W
W
W
R/W R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ₁ and IRQ₀ are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved; they are always read as 1 and cannot be modified.
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; only 0 can be written to these bits.
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