HD6433802H Datasheet, PDF(232/435 Page) Hitachi Semiconductor – Single-Chip Microcomputer

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HD6433802H Datasheet, PDF (232/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

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Input event

IRQAEC or IECPWM

Actually counted clock source

Edge generated by clock return

Counter value N

N+1

N+2

N+3

N+4

N+5

N+6

Clock stopped

Figure 9.11 Example of Clock Control Operation

9.4.4 Asynchronous Event Counter Operation Modes

Asynchronous event counter operation modes are shown in table 9.10.

Table 9.10 Asynchronous Event Counter Operation Modes

Operation

Mode

Reset Active

Sleep

Watch

Subactive Subsleep Standby

Module

Standby

AEGSR Reset Functions Functions Held*1

Functions Functions Held*1

Held

ECCR

Reset Functions Functions Held*1

Functions Functions Held*1

Held

ECCSR Reset Functions Functions Held*1

Functions Functions Held*1

Held

ECH

Reset Functions Functions Functions*1*2 Functions*2 Functions*2 Functions*1*2 Halted

ECL

Reset Functions Functions Functions*1*2 Functions*2 Functions*2 Functions*1*2 Halted

IEQAEC Reset Functions Functions Held*3

Functions Functions Held*3

Held*4

Event

counter

PWM

Reset Functions Functions Held

Held

Held

Held

Held

Notes: 1. When an asynchronous external event is input, the counter increments but the counter

overflow H/L flags are not affected.

2. Operates when asynchronous mode external events are selected; halted and retained

otherwise.

3. Clock control by IRQAEC operates, but interrupts do not.

4. As the clock is stopped in module standby mode, IRQAEC has no effect.

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