HD6433802H Datasheet, PDF (205/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
0
1
Description
Clearing conditions:
After reading CMFL = 1, cleared by writing 0 to CMFL
Setting conditions:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
0
1
Description
TCFL overflow interrupt request is disabled
TCFL overflow interrupt request is enabled
(initial value)
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
0
1
Description
TCFL clearing by compare match is disabled
TCFL clearing by compare match is enabled
(initial value)
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