HD6433802H Datasheet, PDF (254/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
0
ø_w/2^*1/ø_w^*2
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. ø w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. ø w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is øw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Maximum Bit Rate
OSC (MHz)
(bit/s)
n
0.0384*
600
0
2
31250
0
2.4576
38400
0
4
62500
0
10
156250
0
16
250000
0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Setting
N
0
0
0
0
0
0
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