HD6433802H Datasheet, PDF (227/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

9. Event counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin, or ø/2, ø/4, or ø/8, is used as the
input clock source. ECL can be cleared to H'00 by software, and is also initialized to H'00 upon
reset.
Bit
Initial Value
Read/Write
7
ECL7
0
R
6
ECL6
0
R
5
ECL5
0
R
4
ECL4
0
R
3
ECL3
0
R
2
ECL2
0
R
1
ECL1
0
R
0
ECL0
0
R
10. Clock stop register 2 (CKSTPR2)
Bit
7
6
5
4
3
2
1
0
—
—
— PW2CKSTP AECKSTP — PW1CKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
R/W
R/W
—
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
Bit 3: Asynchronous event counter module standby mode control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
0
1
Description
Asynchronous event counter is set to module standby mode
Asynchronous event counter module standby mode is cleared
(initial value)
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