HD6433802H Datasheet, PDF (223/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bits 5 and 4: AEC clock select L (ACKL1, ACKL0)
Bits 5 and 4 select the clock used by ECL.
Bit 5
ACKL1
0
1
Bit 4
ACKL0
0
1
0
1
Description
AEVL pin input
ø/2
ø/4
ø/8
(initial value)
Bits 3 to 1: Event counter PWM clock select (PWCK2, PWCK1, PWCK0)
Bits 3 to 1 select the event counter PWM clock.
Bit 3
PWCK2
0
1
Bit 2
PWCK1
0
1
*
Bit 1
PWCK0
0
1
0
1
0
1
Description
ø/2
ø/4
ø/8
ø/16
ø/32
ø/64
(initial value)
*: Don’t care
Bit 0: Reserved bit
Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Note: Do not set this bit to 1.
7. Event counter control/status register (ECCSR)
Bit
Initial Value
Read/Write
7
6
5
OVH
OVL
—
0
0
0
R/W*
R/W*
R/W
4
3
CH2
CUEH
0
0
R/W
R/W
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
2
CUEL
0
R/W
1
CRCH
0
R/W
0
CRCL
0
R/W
205