HD6433802H Datasheet, PDF (381/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

SCR3—Serial control register3
H'AA
SCI3
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE MPIE TEIE CKE1 CKE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock enable
Bit 1 Bit 0
CKE1 CKE0
0
0
0
1
1
0
1
1
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Description
Clock Source
Internal clock
Internal clock
SCK Pin Function
I/O port
Serial clock output
Internal clock
Clock output
Reserved (Do not specify this combination)
External clock
External clock
Clock input
Serial clock input
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0 Transmit end interrupt request (TEI) disabled
1 Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0 Multiprocessor interrupt request disabled (normal receive operation)
[Clearing conditions]
When data is received in which the multiprocessor bit is set to 1
1 Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0 Receive operation disabled (RXD pin is I/O port)
1 Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0 Transmit operation disabled (TXD pin is transmit data pin)
1 Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0 Transmit data empty interrupt request (TXI) disabled
1 Transmit data empty interrupt request (TXI) enabled
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