HD6433802H Datasheet, PDF (88/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

7. Wakeup Edge Select Register (WEGR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
0
0
0
0
0
0
0
0
R/W
R/W R/W
R/W R/W R/W
R/W R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n: WKPn edge select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
0
1
Description
WKPn pin falling edge detected
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
3.3.3 External Interrupts
There are 11 external interrupts: WKP₇ to WKP₀, IRQ₁ to IRQ₀, and IRQAEC.
1. Interrupts WKP₇ to WKP₀
Interrupts WKP₇ to WKP₀ are requested by either rising or falling edge input to pins WKP₇ to
WKP₀. When these pins are designated as pins WKP₇ to WKP₀ in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP₇ to WKP₀ interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP₇ to WKP₀. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
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