HD6433802H Datasheet, PDF (119/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON bits
in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral
functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
5.2.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer F, asynchronous counter, IRQAEC, IRQ₁,
IRQ₀, WKP₇ to WKP₀, SCI3, A/D converter), or by input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. A
transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of the
condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
Interrupt signal and system clock are mutually asynchronous. Synchronization error time in a
maximum is 2/ø (s).
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
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