HD6433802H Datasheet, PDF (233/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

9.4.5 Application Notes
1. When reading the values in ECH and ECL, first clear bits CUEH and CUEL to 0 in ECCSR to
prevent asynchronous event input to the counter. The correct value will not be returned if the
event counter increments while being read.
2. Use a clock with a frequency of up to 16 MHz for input to the AEVH and AEVL pins, and
ensure that the high and low widths of the clock are at least 30 ns. The duty cycle is
immaterial.
Mode
Active (high-speed), sleep (high-speed)
Active (medium-speed), sleep (medium-speed) (ø/16)
(ø/32)
(ø/64)
f_OSC = 1 MHz to 4 MHz
Watch, subactive, subsleep, standby
(ø/128)
(øw/2)
(øw/4)
øw = 32.768 kHz or 38.4 kHz
(øw/8)
Maximum AEVH/AEVL Pin Input
Clock Frequency
16 MHz
2 · f_OSC
f_OSC
1/2 · f_OSC
1/4 · f_OSC
1000 kHz
500 kHz
250 kHz
3. When AEC uses with 16-bit mode, set CUEH in ECCSR to “1” first, set CRCH in ECCSR to
“1” second, or set both CUEH and CRCH to “1” at same time before clock entry. While AEC
is operating on 16-bit mode, do not change CUEH. Otherwise, ECH will be miscounted up.
4. When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH,
ECPWCRL, ECPWDRH, and ECPWDRL should not be modified.
When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in
AEGSR before modifying these registers.
5. The event counter PWM data register and event counter PWM compare register must be set so
that event counter PWM data register < event counter PWM compare register. If the settings
do not satisfy this condition, do not set ECPWME to 1 in AEGSR.
6. As synchronization is established internally when an IRQAEC interrupt is generated, a
maximum error of 1 tcyc will occur between clock halting and interrupt acceptance.
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