HD6433802H Datasheet, PDF (231/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

toff = T × (Ndr +1)
ton
tcm = T × (Ncm +1)
T_on :
T_off :
T_cm :
T:
Clock input enabled time
Clock input disabled time
One conversion period
ECPWM input clock cycle
N_dr : Value of ECPWDRH and ECPWDRL
Fixed high when Ndr = H'FFFF
N_cm : Value of ECPWCRH and ECPWCRL
Figure 9.10 Event Counter Operation Waveform
Note: N_dr and N_cm above must be set so that N_dr < N_cm. If the settings do not satisfy this
condition, do not set ECPWME to 1 in AEGSR.
Table 9.9 Examples of Event Counter PWM Operation
Conditions: f_osc = 4 MHz, f_ø = 2 MHz, high-speed active mode, ECPWCR value (N_cm) = H'7A11,
ECPWDR value (N_dr) = H'16E3
Clock Source Clock Source ECPWMCR ECPWMDR t_off = T ×
Selection
Cycle (T)*
Value (N_cm) Value (N_dr) (N_dr + 1)
ø/2
1 µs
H'7A11
H'16E3
5.86 ms
ø/4
2 µs
D'31249 D'5859
11.72 ms
t_cm = T ×
(N_cm + 1)
31.25 ms
62.5 ms
t_on = t_cm – t_off
25.39 ms
50.78 ms
ø/8
4 µs
23.44 ms 125.0 ms 101.56 ms
ø/16
8 µs
46.88 ms 250.0 ms 203.12 ms
ø/32
16 µs
93.76 ms 500.0 ms 406.24 ms
ø/64
32 µs
187.52 ms 1000.0 ms 812.48 ms
Note: * t_off minimum width
5. Clock Input Enable/Disable Function Operation
The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in
AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As
this function forcibly terminates the clock input by each signal, a maximum error of one count will
occur depending the IRQAEC or IECPWM timing.
Figure 9.11 shows an example of the operation of this function.
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