HD6433802H Datasheet, PDF (253/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
OSC
10 MHz
16 MHz
B Bit Rate
Error
Error
(bit/s) n N (%) n N (%)
110
2 88 –0.25 2 141 –0.02
150
2 64 0.16 2 103 0.16
200
2 48 –0.35 2 77 0.16
250
2 38 0.16 2 62 –0.79
300
— — — 2 51 0.16
600
— — — 2 25 0.16
1200
0 129 0.16 0 207 0.16
2400
0 64 0.16 0 103 0.16
4800
— — — 0 51 0.16
9600
— — — 0 25 0.16
19200 — — — 0 12 0.16
31250 0 4 0 0 7 0
38400 — — — — — —
Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
OSC
N=
—1
(64 × 2²ⁿ × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of ø_OSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.4.)
3. The error in table 10.3 is the value obtained from the following equation, rounded to two
decimal places.
B (rate obtained from n, N, OSC) — R(bit rate in left-hand column in table 10.3.)
Error (%) =
× 100
R (bit rate in left-hand column in table 10.3.)
235