HD6433802H Datasheet, PDF (85/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

5. Interrupt request register 2 (IRR2)
Bit
7
6
5
IRRDT IRRAD —
Initial value
Read/Write
0
0
—
R/W ^* R/W^* W
4
3
2
1
0
— IRRTFH IRRTFL — IRREC
—
0
0
—
0
W
R/W ^* R/W ^* W
R/W ^*
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer FH, or Timer FL asynchronous event counter interrupt is requested.
The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to
clear each flag.
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
0
1
Description
Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
0
1
Description
Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
(initial value)
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; only 0 can be written to these bits.
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