HD6433802H Datasheet, PDF (257/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10.7 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
0
ø_w/2^*1/ø_w^*2
0
1
2
ø/16
1
0
3
ø/64
1
1
Notes: 1. ø w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. ø w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is øw/2 only.
10.2.9 Clock stop register 1 (CKSTPR1)
Bit
7
—
Initial value
1
Read/Write
—
6
5
4
3
2
1
0
— S32CKSTP ADCKSTP — TFCKSTP — TACKSTP
1
1
1
1
1
1
1
—
R/W
R/W
—
R/W
—
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 5: SCI3 module standby mode control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI3.
S32CKSTP Description
0
SCI3 is set to module standby mode
1
SCI3 module standby mode is cleared
Note: All SCI3 register is initialized in module standby mode.
(initial value)
239