HD6433802H Datasheet, PDF (358/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Addressing Mode/
Instruction Length (bytes)
Condition Code
Mnemonic
Operation
I HNZVC
JSR @Rn
— SP–2 → SP
PC → @SP
PC ← Rn16
2
—————— 6
JSR @aa:16
— SP–2 → SP
PC → @SP
PC ← aa:16
4
—————— 8
JSR @@aa:8
— SP–2 → SP
PC → @SP
PC ← @aa:8
2 —————— 8
RTS
— PC ← @SP
SP+2 → SP
2 —————— 8
RTE
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2
10
SLEEP
— Transit to sleep mode.
2 —————— 2
LDC #xx:8, CCR
B #xx:8 → CCR
2
2
LDC Rs, CCR
B Rs8 → CCR
2
2
STC CCR, Rd
B CCR → Rd8
2
—————— 2
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
2
NOP
— PC ← PC+2
2 —————— 2
EEPMOV
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
4 — — — — — — (4)
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation.
(4) The number of states required for execution is 4n + 9 (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
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