HD6433802H Datasheet, PDF (3/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

List of Items Revised or Added for This Version
Section
1.1 Overview
Page
3
2.8.1 Memory Map 46
47
3.3.1 Overview
60
3.3.2 Interrupt Control 61
Registers
62
63 to 65
65
67, 68
3.3.5 Interrupt
74
Operations
3.4.2 Notes on
79
Rewriting Port Mode
Registers
3.4.3 Interrupt
80
Request Flag Clearing
Methods
4.5 Note on Oscillators 90 to 92
5.1 Overview
95
5.3.3 Oscillator Setting 103
Time after Standby
Mode is Cleared
Item
Description
Table 1.1 Features
Description of time
specification amended
Figure 2.16(2) H8/3801 Memory Figure amended
Map
Figure 2.16(3) H8/3800 Memory Figure amended
Map
Table 3.2 Interrupt Sources and Amended
Their Priorities
Table 3.3 Interrupt Control
Registers
Initial values amended
1. IRQ edge select register (IEGR) Bits 4 to 2 amended
2. Interrupt enable register 1
(IENR1)
Bits 6, 4, and 3 amended
3. Interrupt enable register 2
(IENR2)
Bits 5, 4, and 1 amended
4. Interrupt request register 1
(IRR1)
Bits 6, 4, and 3 amended
5. Interrupt request register 2
(IRR2)
Bits 5, 4, and 1 amended
Figure 3.3 Flow up to Interrupt
Acceptance
Figure amended
Table 3.5 Conditions under which IRREC2 flag condition
Interrupt Request Flag is Set to 1 amended
3.4.3 Interrupt Request Flag
Clearing Method
Description added
4.5.1 Definition of Oscillation
Setting Standby Time
4.5.2 Notes on Use of Crystal
Oscillator Element(Excluding
Ceramic Oscillator Element)
Table 5.2 Internal State in Each
Operating Mode
Table 5.4 Clock Frequency and
Setting Time
Description added
Note 7 amended
Changed