HD6433802H Datasheet, PDF (278/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

• Simultaneous transmit/receive
Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bit SPC32 to
1 in SPCR
Read bit TDRE
1
in SSR
No
TDRE = 1?
Yes
Write transmit
data to TDR
Read bit OER
in SSR
Yes
OER = 1?
No
Read bit RDRF
2
in SSR
No
RDRF = 1?
Yes
Read receive data
in RDR
Overrun error
4
processing
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
2. Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
3. When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
4. If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmis-
sion and reception cannot be resumed if bit
OER is set to 1.
See figure 10-13 for details on overrun error
processing.
3
Continue data
Yes
transmission/reception?
No
Clear bits TE and
RE to 0 in SCR3
End
Figure 10.15 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
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