HD6433802H Datasheet, PDF (83/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Bit 1: Reserved bit
Bit 1 is reserved; only 0 can be written to this bit.
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
0
1
Description
Disables asynchronous event counter interrupt requests
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3 interrupt control, see 10.2.6. Serial control register 3 (SCR3).
4. Interrupt request register 1 (IRR1)
Bit
7
6
5
4
3
2
1
0
IRRTA
—
—
—
— IRREC2 IRRI1 IRRI0
Initial value
0
—
1
—
—
0
0
0
Read/Write
R/W ^*
W
—
W
W
R/W^* R/W ^* R/W^*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
IRQAEC or IRQ₁, IRQ₀ interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
0
1
Description
Clearing conditions:
When IRRTA = 1, it is cleared by writing 0
Setting conditions:
When the timer A counter value overflows from H'FF to H'00
(initial value)
Bits 6, 4, and 3: Reserved bits
Bits 6, 4, and 3 are reserved; only 0 can be written to these bits.
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
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