HD6433802H Datasheet, PDF (411/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

IRR2—Interrupt request register 2
H'F7
Bit
7
6
5
IRRDT IRRAD —
Initial value
0
0
—
Read/Write R/(W)* R/(W)* W
4
3
2
1
0
— IRRTFH IRRTFL — IRREC
—
0
0
—
0
W R/(W)* R/(W)* W R/(W)*
System control
Asynchronous event counter interrupt request flag
0 Clearing conditions:
When IRREC = 1, it is cleared by writing 0
1 Setting conditions:
When the asynchronous event counter value overflows
Timer FL interrupt request flag
0 Clearing conditions:
When IRRTFL = 1, it is cleared by writing 0
1 Setting conditions:
When counter FL and output compare register FL
match in 8-bit timer mode
Timer FH interrupt request flag
0 Clearing conditions:
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When counter FH and output compare register FH match
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
A/D converter interrupt request flag
0 Clearing conditions:
When IRRAD = 1, it is cleared by writing 0
1 Setting conditions:
When the A/D converter completes conversion and
ADSF is reset
Direct transition interrupt request flag
0 Clearing conditions:
When IRRDT = 1, it is cleared by writing 0
1 Setting conditions:
When a SLEEP instruction is executed while DTON is
set to 1, and a direct transition is made
Note: * Bits 7, 6, 3, 2, and 0 can only be written with 0, for flag clearing.
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