HD6433802H Datasheet, PDF (261/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Table 10.9 SMR and SCR3 Settings and Clock Source Selection
SMR SCR3
bit 7 bit 1 bit 0
Transmit/Receive Clock
COM CKE1 CKE0 Mode
Clock Source SCK₃₂ Pin Function
00
0
Asynchronous Internal
I/O port (SCK₃₂ pin not used)
1
mode
Outputs clock with same frequency as bit rate
1
0
External
Inputs clock with frequency 16 times bit rate
10
0
Synchronous Internal
Outputs serial clock
1
0
mode
External
Inputs serial clock
01
1
Reserved (Do not specify these combinations)
10
1
11
1
3. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt Flags Interrupt Request Conditions
Notes
RXI
RDRF When serial reception is performed
The RXI interrupt routine reads the
RIE normally and receive data is transferred receive data transferred to RDR and
from RSR to RDR, bit RDRF is set to 1, clears bit RDRF to 0. Continuous
and if bit RIE is set to 1 at this time, RXI reception can be performed by
is enabled and an interrupt is requested. repeating the above operations until
(See figure 10.2 (a).)
reception of the next RSR data is
completed.
TXI
TDRE When TSR is found to be empty (on The TXI interrupt routine writes the
TIE completion of the previous transmission) next transmit data to TDR and clears
and the transmit data placed in TDR is bit TDRE to 0. Continuous
transferred to TSR, bit TDRE is set to 1. transmission can be performed by
If bit TIE is set to 1 at this time, TXI is repeating the above operations until
enabled and an interrupt is requested. the data transferred to TSR has
(See figure 10.2 (b).)
been transmitted.
TEI
TEND When the last bit of the character in
TEI indicates that the next transmit
TEIE TSR is transmitted, if bit TDRE is set to data has not been written to TDR
1, bit TEND is set to 1. If bit TEIE is set when the last bit of the transmit
to 1 at this time, TEI is enabled and an character in TSR is sent.
interrupt is requested. (See figure 10.2
(c).)
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