HD6433802H Datasheet, PDF (112/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Reset state
Program
halt state
Standby
mode
Watch
mode
inSsLtrEu_*^Ec₄^tPion*d
Program
execution state
Active
(high-speed)
mode
insStrLuEctEioPn _*d
*4
*1
iSnsLtEruEcPtion^*e
*1
Active
(medium-speed)
mode
SLEEP
instruction^*e
*1
Subactive
mode
Program
halt state
SLEEP
instruction^*a
Sleep
*3
iSnLisnEtsruEtrcSPuticLotEni^*_oE^a_nP*b
(high-speed)
mode
SLEEP
instruction^*b
Sleep
*3
(medium-speed)
mode
SLEEP
instruction^*c
*2
Subsleep
mode
Power-down modes
Mode Transition Conditions (1)
Mode Transition Conditions (2)
LSON MSON SSBY TMA3 DTON
a
0
0
0
✻
0
b
0
1
0
✻
0
c
1
✻
0
1
0
d
0
✻
1
0
0
e
✻
✻
1
1
0
f
0
0
0
✻
1
g
0
1
0
✻
1
h
0
1
1
1
1
i
1
✻
1
1
1
j
0
0
1
1
1
* : Don’t care
Interrupt Sources
1 Timer A, Timer F interrupt, IRQ₀ interrupt, WKP₇ to
WKP₀ interrupts
2 Timer A, Timer F, SCI3 interrupt, IRQ₁ and IRQ₀
interrupts, IRQAEC, WKP₇ to WKP₀ interrupts, AEC
3 All interrupts
4 IRQ₁ or IRQ₀ interrupt, WKP₇ to WKP₀ interrupts
Notes: 1.
2.
A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
Details on the mode transition conditions are given in the explanations of each mode,
in sections 5-2 through 5-8.
Figure 5.1 Mode Transition Diagram
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