HD6433802H Datasheet, PDF (308/435 Pages) Hitachi Semiconductor – Single-Chip Microcomputer

12.3 Operation
12.3.1 A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10-
bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2 A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset Active
Sleep
Module
Watch Subactive Subsleep Standby Standby
AMR
Reset Functions Functions Held Held
Held
Held
Held
ADSR Reset Functions Functions Held Held
Held
Held
Held
ADRRH Held* Functions Functions Held Held
Held
Held
Held
ADRRL Held* Functions Functions Held Held
Held
Held
Held
Note: * Undefined in a power-on reset.
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